Workshop on Atomic Layer Processing
Looking back in the evolution of IC technology, it can be stated that from the 0.25µm node on, the key for further shrinking was planarization. This was enabled by the introduction of an emerging technology, the CMP. Since the 28 nm node it can be observed that, at least in the front end of line, starting with the FinFET and possibly continuing with the surrounding gate transistor, the required structures become more and more three dimensional, while the thickness of the associated films become extremely thin (gate dielectric, work function layer, barrier layer). The emerging technology enabling this is Atomic Layer Deposition (ALD).
ALD is based on self limiting heterogeneous chemical reactions which allow the fabrication of very thin (sub nm to few nm) layers with high accuracy (basically atomic layer precision), extremely well conformality and intrinsically high uniformity even in batch tools. Although the scientific background of ALD goes far back in history, ALD for semiconductor processing can still be considered as a novel technology.
Progress in ALD is associated with tools, but even more with specifically designed precursors which need to be applied at optimum conditions of the gas feed system, the process chamber and the substrate condition. Our workshop, which is organized by the “ALD Lab Dresden” wants to stimulate discussions between developers of tools, consumables, as well as applicants of this exciting technology.
The self limiting behavior of the heterogeneous reaction can however also be used to remove material from a substrate in an extremely controlled fashion of atomic dimensions. This process, that can be viewed as the complement to ALD is called Atomic Layer Etching (ALEt). As for ALD also ALEt can be a game changer for the semiconductor industry utilizing surface functionalization and modification similar to those we know in ALD and resulting in a chemistry-based material removal on the same atomic level as in ALD – A layer by layer removal.
In general scaling is thought about to be a shrink in the critical dimensions (CD, pitch) in the latheral xy-plane, today scaling is also taking place in the z-direction, i.e., a reduction in the thickness of the film stacks like the High-k Metal Gate stack. This has resulted in that the thicknesses of the film stacks of devices today are now routinely approaching <20 Å nm providing an opportunity for slow and precise etching by ALEt.
We hope that this new part of the ALD Lab Dresden Symposium will allow for increased scientific and technological discussion for enabling ALEt and learning from ALD and related plasma based processing techniques like Plasma CVD and Reactive Ion Etching.